As the system on a chip becomes faster and larger, it is becoming increasingly difficult to distribute the clock to the entire chip because of clock skew. To achieve a low skew clock distribution, low skew drivers are used which are extremely power hungry. Asynchronous circuits may provide a solution for this problem.
A system is asynchronous if a clock is not used for sequencing actions such that inputs and outputs can change at any time. The chief difficulty in asynchronous design is knowing when a specific computation is complete. However, a major advantage of asynchronous design over synchronous designs is that asynchronous designs dissipate substantially less power than synchronous designs because asynchronous circuits only dissipate power when actively computing instead of for each clock cycle. Thus, less power is used because there is less switching.
Additionally, skew is also not an issue for asynchronous circuits because there is no common clock. Asynchronous circuits are also modular and exhibit average case performance instead of worst case as is the case for synchronous circuits. Asynchronous circuits also exhibit dramatic improvements in terms of electro-magnetic interference and are inherently closed loop making them more robust in the presence of process, voltage, and temperature variations.
Asynchronous design has shown substantial power and performance benefits but is in practice difficult to implement due to the protocol and sequential, rather than combinational, nature of its design. Revolutionary means of designing these chips has largely failed to gain wide spread industry acceptance. Asynchronous designs have been avoided because they are difficult to implement and difficult to test. In general, there is a lack of good computer aided design (CAD) tools that completely cover the design flow for asynchronous circuits.
Desynchronization is an evolutionary means of creating asynchronous designs from clocked circuit design largely using the traditional clocked CAD. In this design style, the clock distribution network is removed and replaced with asynchronous handshake protocols and circuitry. Current means of implementing desynchronization use a static marked graph handshake and token marking with no choice. The handshake protocol guarantees correctness of the clock distribution network but carries no information about data validity. This results in circuits that behave very much like a clocked design, but with a performance and power penalty.